搜索资源列表
counter8
- 基于verilog的8位计数器的编写，有测试程序，并且测试通过-Based on the 8-bit counter verilog preparation, test procedures, and test by
counter
- This is 2-BCD numbers Counter on board Altera DE2 Code Verilog HDL (You must import DE2_pin_assignments.csv to use this code)
verilog-example
- verilog基础实验，包括篮球计数器，序列检测计等-verilog based experiments, including basketball counter sequence detector
The-decimal-counter
- 用verilog实现的十进制计数器(异步复位)-The decimal counters (asynchronous reset)
counter
- A 4 bit counter. In the testbench I combine three counters into one. Verilog codes with testbench.
Decade-Counter
- The file contains source code verilog for counting number of 1s
Johnson-counter-with-verilog-design
- the file contains verilog code for johnson counter
Mod13-counter-with-verilog-design
- verilog code for mod13 counter source code-verilog code for mod13 counter source code
ringcounter-with-verilog-design
- Ring counter souce code in verilog
A-4-bit-variable-modulus-counter
- 用Verilog HDL设计一个4bit变模计数器和一个5bit二进制加法器。在4bit输入cipher的控制下，实现同步模5、模8、模10、模12及用任务调用语句实现的5bit二进制加法器，计数器具有同步清零和暂停计数的功能。主频为50MHz，要求显示频率为1Hz。-A 4-bit variable modulus counter and a 5bit of binary adder using Verilog HDL design. 4bit input under the control
counter
- 计算器的verilog语言程序代码。能实现加、减、乘、除运算。-verilog language of counter。it can achiev plus o, minus, multiplication and addition operations
text9
- 数字电路实验：计数器。使用小规模集成器件设计计数器的；使用中规模集成器件设计计数器的；Verilog HDL对计数器的建模-Digital circuit experiment: Counter. The use of small-scale integrated device design counter Use medium-scale integrated devices designed to counter Verilog HDL modeling counter
counter
- implementation of a four bit counter in verilog
counter
- 采用VERIlOG HDL语言设计的一个加法器项目，简单可靠，并把其中测试平台程序加入其中-VERIlOG HDL language designed using an adder project, simple, reliable, and to join the program in which the test platform
Counter
- 该程序是一个verilog语言程序，用于计数-The program is a verilog language program, used to count
jishuqi
- 4位二进制的计数器 Verilog 代码-4-bit binary counter Verilog code
counter
- 同步清零的可逆计数器，带时钟分频 Verilog HDL语言编写-Synchronous clear reversible counter with clock divider Verilog HDL language
verilog-source-codes
- the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
count_1000
- 适用于verilog hdl初学者——0-999加法计数器，内带vwf波形仿真-Suitable for beginners 0-999 adding counter verilog hdl, which with vwf waveform simulation
counter
- 利用verilog编写的分频计数器，包括0.01s,1ms，1s三个计数器，可适用于ise14.7开发环境-Use verilog to write a crossover counter, including 0.01s, 1ms, 1s three counters, applicable to ise14.7 development environment